Hardware security researcher with 5+ years of experience in secure RTL design, root-of-trust, and obfuscation-based IP protection. Proven contributions in algorithmic and structural attack-resilient hardware IPs, CAD framework (KAVACH), cryptographic architectures, and security-driven ASIC/FPGA flows. Skilled in attack surface evaluation and reduction using formal and simulation-based methods. Development of a security-aware RTL-to-GDSII flow with optimized PPA-security tradeoffs, supported by contributions in flagship international conferences.

• Developed KAVACH: a first-of-its-kind CAD framework for zero-knowledge logic obfuscation integration, enabling automated security primitives integration and adversarial evaluation on benchmark netlist/IPs
• Designed and demonstrated ULTRONE, an effective logic locking attack technique achieving 100% key recovery on sarlock/iolts-protected netlists in seconds, with improved key prediction accuracy and reduced runtime
• Proposed DyLock, a dynamic key-based Boolean satisfiability and structural attacks resilient low-overhead (<6%) logic locking technique that balanced PPA-security tradeoffs with validated effectiveness across standard benchmarks
• Developed a resource-efficient modulo reduction unit for the number theoretic transform (NTT) in Dilithium, a post-quantum cryptographic technique, achieving improved area and logic utilization over state-of-the-art designs

• Proposed gated MUX cascades-based SHAKTI and SHAKTI+ locking schemes — attack-resilient with balanced design overheads under 20% across benchmark netlists; demonstrated key-aliasing effect under power trace analysis
• Proposed LOKI, a lightweight key-driven locking technique for IoT IPs, ensuring secure encryption/decryption with low (2–5%) FPGA resource overhead; validated using GIFT cipher for image security application
• Performed comprehensive cryptanalytic evaluation of lightweight 4-bit S-boxes

• Performed load curve analysis, cost evaluation and reduction studies for mission-critical electrical systems, enabling data-driven energy planning and improved procurement efficiency
• Assisted in site inspections, installation, and commissioning of oil-filled transformers, and contributed to GIS-based utility management using NaVIC for spatial asset tracking

• Graduate Student Member, IEEE (2021 – Present)
• Young Professional, IEEE (2021 – Present)
• IEEE Circuits and Systems Society (CASS) — 2024 – Present
• IEEE Computer Society — 2024 – Present

• Science communicator and technology demonstrator in CSIR outreach program
• Mentoring post-graduate and graduate research scholars
• Attended & volunteered at AESDP Workshop on Advanced Electronics Systems Design, CSIR-CEERI, Pilani

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